The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section. Furthermore, all embodiments of the invention need not solve all (or even any) of the problems brought forward in this section.
Simulation is a key activity performed in the process of taking a hardware design from concept to realization as a semiconductor integrated circuit. Simulation covers many technological aspects that trigger the resulting performances of the design. Simulation has much value for hardware designers as it is used for proving correctness of a design before costly fabrication is launched.
To that end, simulation includes not only verifying the logical correctness of the hardware design, its throughput and latency, for instance, but also its power consumption. Indeed, power consumption has become one of the most critical performance parameters in modern Very Large Scale Integration (VLSI) Integrated Circuits (ICs), due to the continuously increasing power density of modern ICs, defined as the number of transistors per chip. Also, power efficiency has increased in importance in the context of the development of wireless and mobile technologies, which require low power integrated designs for a wide range of battery powered applications.
A hardware design can be simulated at a variety of levels of abstraction. Commonly, a model is simulated at several levels of abstraction in the same simulation run. Known levels of abstraction include Gate Level (GL) and Register Transfer Level (RTL). However, it is possible to incorporate lower levels like transistor level or even lower physical levels, as well as higher levels such as transaction levels or domain-specific levels.
Accurate power estimation can be done on a GL netlist. This estimation provides power data for every instance in the GL netlist. Most of these instances are created by the synthesis tools and do not exist in the RTL netlist.
Significant power optimization, however, can be done in the RTL netlist only, and therefore performing power optimization at GL level does not prove efficient. One option may be to do it by “reverse engineering” of GL power data or just in empiric way, meaning that each RTL change is just simulated for power change.
In addition, most of the synthesis flows “flatten” the RTL netlist, i.e. remove all the RTL hierarchy data from the design. As a result, identifying the power consumption of RTL module based on the GL netlist is not really possible.
One may consider synthesizing the design with strict restrictions on hierarchies, and mapping the power across GL-RTL common hierarchies. This methodology, however, would miss the most of the clock tree which is consumed at the top level, the intra hierarchy connections and the optimization done by the synthesis tool while running on a flat design.
U.S. Pat. No. 6,901,565 and U.S. Pat. No. 6,598,209, assigned to Sequence Design, Inc., disclose a RTL power analysis using GL cell power analysis. It is described therein a method of mapping macro power from GL netlist to RTL netlist. This method, however, requires synthesizing using specific macros and special condition.
U.S. Pat. No. 6,865,722, titled “Method of automating chip power consumption estimation calculation”, describes how to map general power reports to a high level design. The disclosed solution enables mapping power consumption of high level hierarchies only, and does not provide the required granularity of RTL optimization, since data is available only for top level hierarchies and not for flip flop or even RTL sub modules.
US 2008/0010618 A1 discloses a method and a device for designing a semiconductor integrated circuit that reduces off leakage current. Wires connected to input terminals of a standard cell are exchanged with one another and a gate net list is changed so as to reduce off leakage current in accordance with a net probability and a power consumption table. The net probability is the probability of the state an input of the standard cell can take and is generated through an RTL function simulation and a gate level function simulation. This document suggests mapping RTL data to GL netlist.